Current detection circuit and dcdc converter including the same

ABSTRACT

According to an embodiment, a current detection circuit includes a transistor, an operational amplifier, and a transistor. In the transistor, the source and the gate are coupled to the source and the gate of a transistor which is provided on a high side of a drive circuit. The operational amplifier amplifies a potential difference between a drain voltage of the transistor and a drain voltage of the transistor. The transistor is provided over a current path through which a current flowing to the transistor flows, and which has the gate to which an output voltage of the operational amplifier is supplied. A value of the current flowing through the transistor is detected based on a value of the current flowing through the transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of U.S. patent application Ser. No.15/461,687, filed on Mar. 17, 2017, which claims benefit to JapanesePatent Application No. 2016-057925, filed on Mar. 23, 2016 including thespecification, drawings and abstract are incorporated herein byreference in their entirety.

The present invention relates to a current detection circuit and a DCDCconverter including the circuit, and relates, for example, to a currentdetection circuit capable of cost reduction and a DCDC converterincluding the circuit.

BACKGROUND

U.S. Pat. No. 6,377,034 discloses a configuration of a current detectioncircuit which detects a current flowing through a drive circuit.

Specifically, the current detection circuit is a circuit for detecting acurrent flowing through an N-channel drive transistor provided on a highside of the drive circuit. The current detection circuit has at least asense transistor, an operational amplifier, and a transistor. The sensetransistor has a drain and a gate which are coupled respectively to adrain and a gate of the drive transistor. The operational amplifieramplifies a potential difference between a source voltage of the sensetransistor and a source voltage of the drive transistor. The transistoris coupled in series with the sense transistor, and has a gate to whichan output voltage of the operational amplifier is supplied.

A gate-source voltage and a drain-source voltage of the sense transistorrespectively indicate the same values as a gate-source voltage and adrain-source voltage of the drive transistor. Thus, through the sensetransistor, a current (for example, a current of one thousandth)proportional to a current flowing through the drive transistor flows.The current detection circuit detects the current flowing through thesense transistor, thereby enabling to detect with high accuracy thecurrent (more specifically, the current flowing between the drain andthe source of the drive transistor) flowing through the drive circuit.

SUMMARY

In the configuration of the current detection circuit disclosed in U.S.Pat. No. 6,377,034, if a switching frequency of the drive transistorprovided in the drive circuit is high, a voltage supplied to an inputterminal of the operational amplifier is quickly switched between theground voltage and the input voltage. Thus, the operational amplifier isrequired to perform a very high-speed operation. In the currentdetection circuit disclosed in U.S. Pat. No. 6,377,034, the expensiveoperational amplifier applicable to the high-speed operation isnecessary. This results in an increase in the manufacturing cost. Otherobjects and new features will be apparent from the descriptions of thepresent specification and the accompanying drawings.

According to an embodiment, there is provided a current detectioncircuit including: a first sense transistor which includes a firstterminal and a control terminal which are coupled respectively to afirst terminal provided on an external output terminal side outputtingexternally an output voltage of the drive circuit and a controlterminal, of terminals of a first drive transistor provided on a highside of a drive circuit, the first sense transistor being a sameconductive type as the first drive transistor; a first operationalamplifier which amplifies a potential difference between a voltage of asecond terminal provided on an external input terminal side to which aninput voltage is supplied externally from the drive circuit and avoltage of a second terminal of the first sense transistor, of theterminals of the first drive transistor; and a first current controltransistor which is provided over a first current path through which acurrent from the first sense transistor flows, and which has a controlterminal to which an output voltage of the first operational amplifieris supplied. A value of a current flowing through the first drivetransistor is detected from a value of the current flowing through thefirst sense transistor.

According to an embodiment, there is provided a current detectioncircuit comprising: an N-channel first sense transistor having a sourceand a gate which are coupled respectively to a source and a gate of anN-channel first drive transistor provided on a high side of a drivecircuit; a first operational amplifier which amplifies a potentialdifference between a drain voltage of the first drive transistor and adrain voltage of the first sense transistor; and a first current controltransistor which is provided over a first current path through which acurrent flowing through the first sense transistor flows, and which hasa gate to which an output voltage of the first operational amplifier issupplied. A value of a current flowing through the first drivetransistor is detected based on a value of the current flowing throughthe first sense transistor.

According to the embodiment, it is possible to provide a currentdetection circuit which can suppress an increase in the manufacturingcost and a DCDC converter including the same.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a configuration example of a currentdetection circuit according to an embodiment 1.

FIG. 2 is a diagram illustrating a configuration example of a DCDCconverter over which the current detection circuit illustrated in FIG. 1is mounted.

FIG. 3 is a timing chart illustrating an operation of the DCDC converterillustrated in FIG. 2.

FIG. 4 is a diagram illustrating a first modification of the currentdetection circuit illustrated in FIG. 1.

FIG. 5 is a diagram illustrating a second modification of the currentdetection circuit illustrated in FIG. 1.

FIG. 6 is a diagram illustrating a third modification of the currentdetection circuit illustrated in FIG. 1.

FIG. 7 is a diagram illustrating a configuration example of a currentdetection circuit according to an embodiment 2.

FIG. 8 is a diagram illustrating a concrete configuration of a mixerprovided in the current detection circuit illustrated in FIG. 7.

FIG. 9 is a timing chart illustrating an operation of the mixerillustrated in FIG. 8.

FIG. 10 is a diagram illustrating a configuration example of a DCDCconverter over which the current detection circuit illustrated in FIG. 7is mounted.

FIG. 11 is a timing chart illustrating an operation of the DCDCconverter illustrated in FIG. 10.

FIG. 12 is a diagram illustrating a first modification of the currentdetection circuit illustrated in FIG. 7.

FIG. 13 is a diagram illustrating a second modification of the currentdetection circuit illustrated in FIG. 7.

FIG. 14 is a diagram illustrating a third modification of the currentdetection circuit illustrated in FIG. 7.

FIG. 15 is a diagram illustrating a configuration example of a DCDCconverter according to an embodiment 3.

DETAILED DESCRIPTION

Preferred embodiments will hereinafter be described with reference tothe accompanying drawings. The simplified drawings are given, and thetechnical range of the preferred embodiments is not to be narrowlyinterpreted based on the drawings. The same elements are identified bythe same reference numerals, and thus will not be described repeatedlyover and over.

In the following preferred embodiments, if necessary for conveniencesake, descriptions will be made to divided plural sections or preferredembodiments, however, unless otherwise specified, they are not mutuallyirrelevant, but one is in relations of modifications, applicationexamples, details, supplementary explanations of a part or whole of theother. Further, in the following preferred embodiments, in the case ofreference to the number of an element (including quantity, numericvalue, amount, range), unless otherwise specified and unless clearlylimited in principle, the present invention is not limited to thespecified number, and a number over or below the specified one may beused.

In the following preferred embodiments, the constituent elements(including operation steps) are not necessarily indispensable, unlessotherwise specified and unless considered that they are obviouslyrequired in principle. Similarly, in the following preferredembodiments, in the reference of the forms of the constituent elementsor the positional relationships, they intend to include thoseapproximating or similar substantially to the forms and like, unlessotherwise specified and unless considered that they are obviously notrequired in principle. This is also true of the foregoing numericalvalues (including quantity, numeric value, amount, range).

Embodiment 1

FIG. 1 is a block diagram illustrating a current detection circuit 10according to an embodiment 1. The current detection circuit 10 accordingto this embodiment is a circuit for detecting a current flowing betweenthe drain and the source of an N-channel drive transistor provided onthe high side of a drive circuit.

As illustrated in FIG. 1, the current detection circuit 10 includestransistors MN1 to MN3 and MP1 to MP4, an operational amplifier (a firstoperational amplifier) A1, a resistance element R1, and a regulator RG1.FIG. 1 also illustrates transistors Tr1 and Tr2 and an inductor L1, as apart of the constituent elements provided in the drive circuit 12.

The drive circuit 12 is a circuit for driving an input voltage Vin andoutputting an output voltage Vout, and is provided at an output stage ofa step-down DCDC converter which uses, for example, a peak current modecontrol system.

In the drive circuit 12, the transistor Tr1 is a drive transistor (afirst drive transistor) provided on the high side of the drive circuit12, and is configured with a high withstand voltage N-channel MOStransistor. The transistor Tr2 is a drive transistor (a second drivetransistor) provided on the low side of the drive circuit 12, and isconfigured with a high withstand voltage N-channel MOS transistor.

More specifically, in the transistor Tr1, the drain (a second terminal)is coupled to an input terminal IN, the source (a first terminal) iscoupled to one end (a node N1) of the inductor L1, and a pulse signal Pis supplied to the gate (a control terminal) from a control unit (notillustrated). In the transistor Tr2, the drain (a second terminal) iscoupled to the node N1, the source (a first terminal) is coupled to aground voltage terminal GND, and a pulse signal P2 is supplied to thegate (a control terminal) from a control unit (not illustrated). Aninput voltage Vin is supplied externally to the input terminal IN, and aground voltage GND is supplied to the ground voltage terminal GND. Theother end (a node N2) of the inductor is coupled to an output terminalOUT. The output terminal OUT externally (load) outputs an output voltageVout.

In the drive circuit 12, the transistors Tr1 and Tr2 are controlled tobe turned ON/OFF complementarily based on the dead time existingtherebetween. For example, first, the transistor Tr1 is turned ON, andthe transistor Tr2 is turned OFF. Then, a current flows from the inputterminal IN toward the output terminal OUT through the transistor Tr1and the inductor L1. At this time, the inductor L1 is charged withcurrent energy. After this, the transistor Tr1 is turned OFF, and thetransistor Tr2 is turned ON. As a result, the current flowing from theinput terminal IN to the inductor L1 through the transistor Tr1 is cutoff. To maintain a current value of the previously flowing current, theinductor L1 discharges the charged current energy toward the outputterminal OUT. This causes a current to flow from the ground voltageterminal GND to the output terminal OUT through the transistor Tr2. Byrepeating this operation, the drive circuit 12 outputs an output voltageVout which is obtained by stepping down the input voltage Vin by acertain level corresponding to a duty ratio of a pulse signal.

In the current detection circuit 10, the transistor (a first sensetransistor) MN1 is configured with a high withstand voltage N-channelMOS transistor, like the transistor Tr1. For example, the transistorsize of the transistor MN1 is one thousandths of the transistor size ofthe transistor Tr1.

The transistor MN1 is provided over a current path (a first currentpath) between a high voltage terminal INX to which a voltage VinX higherthan the input voltage Vin is supplied and the source (the node N1) ofthe transistor Tr1. To its gate, a pulse signal P1 is supplied.

The operational amplifier A1 operates, upon supplying the input voltageVin as a low potential side source voltage and a voltage (a firstvoltage) Vhigh higher than the input voltage Vin as a high potentialside source voltage. The amplifier amplifies a potential differencebetween the drain voltage (that is, the input voltage Vin) of thetransistor Tr1 and the drain voltage of the transistor MN1.

In this case, the operational amplifier A1 does not amplify thepotential difference between the source voltage of the transistor Tr1and the source voltage of the transistor MN1, but amplifies thepotential difference between the drain voltage of the transistor Tr1 andthe drain voltage of the transistor MN1. As a result, even when thetransistor Tr1 is switched between ON/OFF states quickly, the voltage tobe supplied to the input terminal of the operational amplifier A1 is notquickly switched. Thus, the operational amplifier A1 is not required toperform a high-speed operation. The current detection circuit 10 doesnot need to use the expensive operational amplifier applicable to thehigh-speed operation, thereby enabling to suppress the increase in themanufacturing cost.

It is adjusted that the potential difference between the high potentialside source voltage (the voltage Vhigh) and the low potential sidesource voltage (the input voltage Vin) supplied to the operationalamplifier A1 becomes equal to or lower than the withstand voltage ofeach transistor included in the operational amplifier A1. Specifically,it is adjusted by controlling the value of the voltage Vhigh generatedby the regulator RG1. Therefore, it is not limited that the operationalamplifier A1 is configured with the high withstand voltage transistor,and it is possible that the amplifier is configured with the lowwithstand voltage transistor. This enables to improve the accuracy orthe operational speed of the operational amplifier A1.

The output voltage of the operational amplifier A1 is supplied to thegate of the transistor (a first current control transistor) MN2. Thetransistor MN2 is configured with a low withstand voltage N-channel MOStransistor, and is provided in series with the transistor MN1 over thecurrent path between the high voltage terminal INX and the node N1. Inthis case, the drain voltage of the transistor Tr1 is mirrored to thedrain voltage of the transistor MN1.

The gate-source voltage and the drain-source voltage of the transistorMN1 indicate the same values as the gate-source voltage and thedrain-source voltage of the transistor Tr1. Thus, between the drain andthe source of the transistor MN1, a current (in this example, a currentof one thousandth) proportional to a current flowing between the drainand the source of the transistor Tr1 flows with high accuracy.

The transistor MN3 is configured with a high withstand voltage N-channelMOS transistor, and is provided in series with the transistor MN2. Avoltage Vhigh is supplied to the gate of the transistor MN3 from theregulator RG1. The transistor MN3 is provided for preventing applicationof a voltage greater than a withstand voltage to the transistor MN2.Thus, when the transistor MN2 is configured with a high withstandtransistor, the transistor MN3 is not necessarily provided.

A transistor MP2 is configured with a low withstand voltage P-channelMOS transistor, and is provided in series with the transistors MN1 toMN3. A transistor MP4 is configured with a low withstand voltageP-channel MOS transistor, and is provided over a current path betweenthe high voltage terminal INX and the ground voltage terminal GND as acurrent path different from the transistor MP2. The gate of thetransistor MP4 is coupled to the drain and the gate of the transistorMP2. Thus, between the drain and the source of the transistor MP4, acurrent proportional to the current flowing between the drain and thesource of the transistor MP2 flows. That is, the transistors MP2 and MP4are included in a current mirror circuit.

The transistor MP1 is configured with a high withstand voltage P-channelMOS transistor, and provided in series with the transistor MP2 and alsothe transistors MN1 to MN3. The transistor MP3 is configured with a highwithstand voltage P-channel MOS transistor, and is provided in serieswith the transistor MP4. The gate of the transistor MP3 is coupled tothe drain and the gate of the transistor MP1. Between the drain and thesource of the transistor MP3, a current proportional to the currentflowing between the drain and the source of the transistor MP1 flows.That is, the transistors MP1 and MP3 are included in a current mirrorcircuit. The transistors MP1 and MP3 are provided for preventingapplication of a voltage greater than a withstand voltage respectivelyto the transistors MP2 and MP4. Thus, when the transistors MP2 and MP4are configured with a high withstand voltage transistor, the transistorsMP1 and MP3 are not necessarily provided.

The resistance element R1 is provided in series with the transistors MP3and MP4. Through the resistance element R1, a current proportional tothe current flowing through the transistor MN1 flows. Through thetransistor MN1, a current proportional to the current flowing throughthe transistor Tr1 flows. Thus, through the resistance element R1, acurrent proportional to the current flowing through the transistor Tr1flows. As a result, it is possible to obtain a value of the currentflowing through the transistor Tr1, from a voltage (a voltage of a nodeN4 between the drain and the resistance element R1 of the transistorMP3) generated based on a value of the current flowing through theresistance element R1 and a resistance value of the resistance elementR1. The voltage of this node N4 is output to the outside of the currentdetection circuit 10 as a detection result Vcs.

In this manner, in the current detection circuit 10 according to thisembodiment, the operational amplifier A1 does not amplify the potentialdifference between the source voltage of the transistor Tr1 and thesource voltage of the transistor MN1, but amplifies the potentialdifference between the drain voltage of the transistor Tr1 and the drainvoltage of the transistor MN1. Even when the transistor Tr1 is switchedbetween ON/OFF states quickly, the voltage to be supplied to the inputterminal of the operational amplifier A1 is not quickly switched. Thus,the operational amplifier A1 is not required to perform a high-speedoperation. The current detection circuit 10 does not need to use theexpensive operational amplifier applicable to the high-speed operation,thereby enabling to suppress the increase in the manufacturing cost.

In the current detection circuit 10 according to this embodiment, it isadjusted that the potential difference between the high potential sidesource voltage (the voltage Vhigh) and the low potential side sourcevoltage (the input voltage Vin) supplied to the operational amplifier A1becomes equal to or lower than the withstand voltage of each transistorincluded in the operational amplifier A1. Therefore, it is not limitedthat the operational amplifier A1 is configured with the high withstandvoltage transistor, and it is possible that the amplifier is configuredwith the low withstand voltage transistor. This enables to improve theaccuracy or the operational speed of the operational amplifier A1.

(Application Example of Current Detection Circuit 10)

FIG. 2 is a diagram illustrating a configuration example of a step-downDCDC converter 1 over which the current detection circuit 10 is mounted.FIG. 3 is a timing chart illustrating an operation of the DCDC converter1. The DCDC converter 1 uses a peak current mode control system as onecontrol system for the output voltage.

As illustrated in FIG. 2, the DCDC converter 1 includes a currentdetection circuit 10, a drive circuit 12, and a control unit 11. Thedrive circuit 12 has transistors Tr1 and Tr2, an inductor L1, acapacitance element C1, and resistance elements R11 and R12. The controlunit 11 has an error amplifier EA1, capacitance elements C2 and C3, aresistance element R3, a comparator CMP1, a latch circuit LAT1, a bufferBF1, and an inverter INV1.

In the drive circuit 12, the capacitance element C1 is provided betweenthe output terminal OUT and the ground voltage terminal GND. Theresistance elements R11 and R12 are provided in series between theoutput terminal OUT and the ground voltage terminal GND. A voltage Vfbof the node N3 between the resistance elements R11 and R12 is obtainedby the resistance elements R11 and R12 dividing the output voltage Vout,and is fed back to the control unit 11. Any other configurations of thedrive circuit 12 are as described above. The operation of the drivecircuit 12 is also as described above.

The current detection circuit 10 detects the current flowing through thetransistor Tr1 provided on the high side of the drive circuit 12, asdescribed above, and outputs a detection result Vcs. The detectionresult Vcs is fed back to the control unit 11.

In the control unit 11, the error amplifier EA1 amplifies a potentialdifference between a reference voltage Vref and a voltage Vfb fed backfrom the drive circuit 12, to generate a voltage Vc. The voltage Vc isintegrated by the capacitance element C2 provided between the outputterminal and the ground voltage terminal GND of the error amplifier EA1or by the capacitance element C3 and the resistance element R3 which areprovided in series between the output terminal and the ground voltageterminal GND of the error amplifier EA1.

For example, when the output voltage Vout decreases, and when thevoltage Vfb is lower than the reference voltage Vref, the output voltageVc of the error amplifier EA1 increases at the rate proportional to thepotential difference between the voltage Vfb and the reference voltageVref. On the contrary, when the output voltage Vout increases, and whenthe voltage Vfb is higher than the reference voltage Vref, the outputvoltage Vc of the error amplifier EA1 decreases at the rate proportionalto the potential difference between the voltage Vfb and the referencevoltage Vref. In the example of FIG. 3, the potential difference betweenthe output voltage Vout and the reference voltage Vref is small. Thus,the output voltage Vc of the error amplifier EA1 indicates a constantvalue.

The comparator CMP1 compares an output voltage (a reference voltage forthe comparator CMP1) of the error amplifier EA1 with the detectionresult Vcs of the current detection circuit 10, and outputs a comparisonresult VR. In the latch circuit LAT1, a clock signal CLK is supplied toa set terminal S, the comparison result VR of the comparator CMP1 issupplied to a reset terminal R, and an output terminal Q outputs asignal Vbuck. The buffer BF1 outputs the signal Vbuck as is as a pulsesignal P1. The inverter INV1 inverts the signal Vbuck, and outputs it asa pulse signal P2.

With reference to FIG. 3, when the transistor Tr1 is turned OFF, thepotential of the detection result Vcs indicates OV. Thus, the comparatorCMP1 outputs a comparison result VR with an L level. At this time, thelatch circuit LAT1 causes the signal Vbuck to rise in synchronizationwith rising of the clock signal CLK. As a result, the transistor Tr1 isturned ON, and the transistor Tr2 is turned OFF. When the transistor Tr1is turned ON, a current flows between the drain and the source of thetransistor Tr1. Thus, the potential of the detection result Vcsincreases in proportion to the elapse of the time in which the currentflows. When the detection result Vcs reaches the voltage Vc, thecomparator CMP1 causes the comparison result VR to be switched from theL level to the H level. At this time, the latch circuit LAT1 causes thesignal Vbuck to rise in synchronization with rising of the comparisonresult VR. As a result, the transistor Tr1 is turned ON, and thetransistor Tr2 is turned ON. When the transistor Tr1 is turned OFF, thepotential of the detection result Vcs indicates OV. Thus, the comparisonresult VR of the comparator CMP1 is soon switched from the H level tothe L level. By repeating this operation, the DCDC converter 1 stepsdown the input voltage Vin to a desired level, and outputs it as anoutput voltage Vout.

This DCDC converter 1 is mounted, for example, over the vehicles. Inrecent years, it is demanded that the DCDC converter mounted over thevehicle perform a high speed switching operation. Thus, it is effectiveto apply the current detection circuit 10 without being effected by thehigh speed switching operation. Further, the current detection circuit10 can realize the operation with high accuracy by using the operationalamplifier A1 configured with a low withstand transistor. In this case,it is possible to design the DCDC converter 1 on the assumption that theaccuracy variation is small. The DCDC converter 1 can increase the loopband.

Subsequently, descriptions will hereinafter be made to somemodifications of the current detection circuit 10.

(First Modification of Current Detection Circuit 10)

FIG. 4 is a diagram illustrating a first modification of the currentdetection circuit 10 as a current detection circuit 10 a.

As compared with the current detection circuit 10 illustrated in FIG. 1,the current detection circuit 10 a illustrated in FIG. 4 further has acurrent path (a third current path) for discharging a current flowingfrom the source to the drain of the transistor MN1, between the drainand the ground voltage terminal GND of the transistor MN1.

More specifically, there is provided a constant current source (a firstconstant current source) CC1 for causing a constant current to flow fromthe drain to the ground voltage terminal GND of the transistor MN1,between the drain and the ground voltage terminal GND of the transistorMN1. Any other configurations of the current detection circuit 10 a arethe same as those of the current detection circuit 10, and thus will notbe described repeatedly over and over.

By the effect of an offset voltage of the operational amplifier A1, thedrain voltage of the transistor MN1 may undesirably be lower than thesource voltage. If there is not provided a current path for dischargingthe current flowing from the source to the drain of the transistor MN1,no current flows from the source to the drain of the transistor MN1,thereby not enabling to perform current detection in consideration ofthe offset voltage.

The current detection circuit 10 a has a current path provided fordischarging the current flowing from the source to the drain of thetransistor MN1. In this configuration, when the drain voltage of thetransistor MN1 is lower than the source voltage by the effect of theoffset voltage, the current detection circuit 10 a can cause the currentto flow from the source to the drain of the transistor MN1, therebyenabling to perform current detection in consideration of the offsetvoltage.

(Second Modification of Current Detection Circuit 10)

FIG. 5 is a diagram illustrating a second modification of the currentdetection circuit 10 as a current detection circuit 10 b.

As compared with the current detection circuit 10 illustrated in FIG. 1,the current detection circuit 10 b illustrated in FIG. 5 furtherincludes a resistance element (a first resistance element) R2 and aswitch element (a first switch element) SW1.

The resistance element R2 and the switch element SW1 are provided inseries between two input terminals of the operational amplifier A1. Theswitch element SW1 is turned ON/OFF based on an inverted signal P1B ofthe pulse signal P1. That is, the switch element SW is controlled to beturned ON/OFF complementarily with the transistors Tr1 and MN1. Forexample, the resistance value of the resistance element R2 indicates thesame value as the resistance value at the time the transistor MN1 is ON.Any other configurations of the current detection circuit 10 b are thesame as those of the current detection circuit 10, and thus will not bedescribed repeatedly over and over.

Even if the transistor MN1 is turned OFF, the load of the operationalamplifier A1 by the resistance element is constantly maintained, becausethe switch element SW1 is turned ON. As a result, the current detectioncircuit 10 b can suppress the settling time of the operational amplifierA1 after the transistor MN1 is switched between ON/OFF states, therebyrealizing the high speed operation.

There may be provided a transistor which is controlled to be turnedON/OFF complementarily with the transistor MN1, instead of theresistance element R2 and the switch element SW1. This transistor isconfigured with a high withstand voltage N-channel MOS transistor havingthe same size as, for example, the transistor MN1.

(Third Modification of Current Detection Circuit 10)

FIG. 6 is a diagram illustrating a third modification of the currentdetection circuit 10 as a current detection circuit 10 c.

As compared with the current detection circuit 10 illustrated in FIG. 1,the current detection circuit 10 c illustrated in FIG. 6 furtherincludes a current path including a constant current source CC1 betweenthe drain and the ground voltage terminal GND of the transistor MN1. Thecircuit 10 c also includes the resistance element R2 and the switchelement SW1 which are provided in series between two input terminals ofthe operational amplifier A1. That is, the current detection circuit 10c includes the constituent element added into the current detectioncircuit 10 a and the constituent element added into the currentdetection circuit 10 b.

Even when the drain voltage of the transistor MN1 is lower than thesource voltage by the effect of the offset voltage, the current can flowfrom the source to the drain of the transistor MN1, and the currentdetection circuit 10 c can perform current detection in consideration ofthe offset voltage. The current detection circuit 10 c can suppress thesettling time of the operational amplifier A1 after the transistor MN1is switched to be turned ON/OFF, thereby realizing the high speedoperation.

Embodiment 2

FIG. 7 is a diagram illustrating a configuration example of a currentdetection circuit 20 according to an embodiment 2. The current detectioncircuit 20 according to the embodiment 2 detects a current flowingthrough the transistor Tr1 provided on the high side of the drivecircuit, and detects a current flowing through the transistor Tr2provided on the low side of the drive circuit, thereby detecting thecurrent flowing through the inductor L1. Specific descriptions willhereinafter be made.

As described in FIG. 7, the current detection circuit 20 includestransistors MN1 to MN5 and MP1 to MP8, operational amplifiers A1 and A2,a mixer MX1, a resistance element R2, a switch element SW1, a constantcurrent source CC1, and a regulator RG1. FIG. 7 illustrates thetransistors Tr1 and Tr2, and the inductor L1, as a part of theconstituent elements provided in a drive circuit 22.

The drive circuit 22 is a circuit which drives an input voltage Vin, andoutputs an output voltage Vout, and provided at the output stage of astep-up/step-down DCDC converter which uses, for example, an averagecurrent mode control system. The configurations of the transistors Tr1and Tr2 and the inductor L1 in the drive circuit 22 are the same asthose of the transistors Tr1 and Tr2 and the inductor 11 in the drivecircuit 12, and thus will not be described repeatedly over and over.

Of the circuit configuration of the current detection circuit 20, theconfiguration of the circuit detecting a current flowing through thetransistor Tr1 provided on the high side of the drive circuit 22 is thesame as the configuration of the current detection circuit 10 c. Thus,of the circuit configuration of the current detection circuit 20,descriptions will hereinafter be made to the configuration of thecircuit detecting a current flowing through the transistor Tr2 providedon the low side of the drive circuit 22.

In the current detection circuit 20, a transistor (a second sensetransistor) MN4 is configured with a high withstand voltage N-channelMOS transistor, like the transistor Tr2. For example, the transistorsize of the transistor MN4 is one thousandth of the transistor size ofthe transistor Tr2.

The transistor MN4 is provided over a current path (a second currentpath) between a source voltage terminal (hereinafter referred to as asource voltage terminal VDD) to which a source voltage VDD is suppliedand the drain (a node N1) of the transistor Tr2. A pulse signal P2 issupplied to the gate of the transistor MN4.

The operational amplifier (the second operational amplifier) A2amplifies a potential difference between a source voltage (that is, theground voltage GND) of the transistor Tr2 and a source voltage of thetransistor MN4. The operational amplifier A2 is configured with a lowwithstand voltage transistor.

The operational amplifier A2 amplifies the potential difference betweenthe source voltage of the transistor Tr2 and the source voltage of thetransistor MN4, instead of amplifying the potential difference betweenthe drain voltage of the transistor Tr2 and the drain voltage of thetransistor MN4. Even when the transistor Tr2 is switched to be turnedON/OFF at high speed, the operational amplifier A2 is not required toperform a high-speed operation, because the voltage supplied to theinput terminal of the operational amplifier A2 is not quickly switched.As a result, the current detection circuit 20 does not use an expensiveoperational amplifier applicable to the high-speed operation, therebyenabling to suppress an increase in the manufacturing cost.

The output voltage of the operational amplifier A2 is supplied to thegate of the transistor (a second current control transistor) MN5. Thetransistor MN5 is configured with a low withstand voltage N-channel MOStransistor, and is provided in series with the transistor MN4 over thecurrent path between the source voltage terminal VDD and the node N1. Asa result, the source voltage of the transistor Tr2 is mirrored to thesource voltage of the transistor MN4.

A gate-source voltage and a drain-source voltage of the transistor MN4respectively indicate the same values as the gate-source voltage and thedrain-source voltage of the transistor Tr2. Therefore, a current (inthis example, a current of one thousandth) proportional to the currentflowing between the drain and the source of the transistor Tr2 flowswith high accuracy between the drain and the source of the transistorMN4.

The transistors MP5 and MP6 are configured both with a low withstandvoltage P-channel MOS transistor, and are provided in series with thetransistor MN5. The transistors MP7 and MP8 are configured both with alow withstand voltage P-channel MOS transistor, and are provided inseries over a current path between the source voltage terminal VDD andthe mixer MX1 as a current path different from that of the transistorsMP5 and MP6. A bias voltage Vbias is supplied to the gates of therespective transistors MP5 and MP7. Further, the gate of the transistorMP8 is coupled to the gate of the transistor MP6 and the drain of thetransistor MP5. Through the transistors MP7 and MP8, a currentproportional to the current flowing through the transistors MP5 ad MP6flows. That is, the transistors MP5 to MP8 are included in a currentmirror circuit.

The mixer MX1 converts a current into a voltage, and outputs it as adetection result Vcs. This current has been obtained by mixing thecurrent (the current of the node N4) flowing through the transistors MP3and MP4 and the current (the current of the node N5) flowing through thetransistors MP7 and MP8.

(Concrete Configuration Example of Mixer MX1)

FIG. 8 is a diagram illustrating a concrete configuration of the mixerMX1.

As illustrated in FIG. 8, the mixer MX1 includes switch elements SW21 toSW25, resistance elements R21 to R23, and a capacitance element C21. Theresistance value of the resistance elements R21 to R23 indicates thesame value.

The switch element SW21 and the resistance element R21 are provided inseries between the drain (a node N5) and the ground voltage terminal GNDof the transistor MP7. The switch element SW21 is controlled to beturned ON/OFF based on an inverted signal P2B of a pulse signal P2. Theswitch element SW22 is provided between the node N5 and the outputterminal (a node N6) of the mixer MX1. The switch element SW22 iscontrolled to be turned ON/OFF based on the pulse signal P2. The switchelement SW23 is provided between the node N4 and the node N6. The switchelement SW23 is controlled to be turned ON/OFF based on the pulse signalP1. The resistance element R22 and the switch element SW25 are providedin series between the node N6 and the ground voltage terminal GND. Theswitch element SW25 is controlled to be turned ON/OFF based on a pulsesignal PSL. The switch element SW24 and the resistance element R23 areprovided in series between the drain (the node N4) and the groundvoltage terminal GND of the transistor MP3. The switch element SW24 iscontrolled to be turned ON/OFF based on the inverted signal P1B of thepulse signal P1. The capacitance element C21 is provided between thenode N6 and the ground voltage terminal GND.

FIG. 9 is a timing chart illustrating a switching operation of the mixerMX1.

As illustrated in FIG. 9, the pulse signal P1 rises after the elapse ofa predetermined period (referred to as a dead time), after the pulsesignal P2 falls. Similarly, the pulse signal P2 rises after the elapseof the dead time, after the pulse signal P1 falls. This can prevent thatthe transistors Tr1 and Tr2 are instantaneously turned ON at the sametime.

The pulse signals P1 and P2 are switched between the H level and the Llevel complementarily based on the dead time existing therebetween. Thepulse signals P1B and P2B are inverted signals of the respective pulsesignals P1 and P2. The pulse signal PSL indicates the L level during thedead time period, and indicates the H level during any other times.

For example, when the pulse signal P1 indicates the H level, and whenthe pulse signal P2 indicates the L level, a current flows through thetransistor Tr1, and no current flows through the transistor Tr2. Acurrent is supplied from the node N4 to the mixer MX1, and no currentflows from the node N5 to the mixer MX1. In the mixer MX1, the switchelements SW21, SW23, and SW25 are turned ON, while the switch elementsSW22 and SW24 are turned OFF. The current supplied from the node N4flows through the ground voltage terminal GND via the switch elementSW23, the resistance element R22, and the switch element SW25. Thevoltage of the node N6 is output as a detection result Vcs. This voltageis generated based on a value of the current flowing from the node N4 tothe resistance element R22 and a resistance value of the resistanceelement R22.

Because the switch element SW21 is ON, the resistance element R21 iscoupled to the node N5 with no current flowing therethrough. Even whenthe switch element SW21 is turned OFF next time, and when the switchelement SW22 is turned ON, it is possible to have a constant load of thenode N5 by the resistance element.

For example, when the pulse signal P2 indicates the H level, and whenthe pulse signal P1 indicates the L level, a current flows through thetransistor Tr2, and no current flows through the transistor Tr1. Thus, acurrent is supplied from the node N5 to the mixer MX1, and no current issupplied from the node N4 to the mixer MX1. In this case, in the mixerMX1, the switch elements SW22, SW24, and the SW25 are turned ON, whilethe switch elements SW21 and SW23 are OFF. As a result, a currentsupplied from the node N5 flows through the ground voltage terminal GNDthrough the switch element SW22, the resistance element R22, and theswitch element SW25. Then, a voltage of the node N6 is output as adetection result Vcs. This voltage is generated based on a value of thecurrent flowing through the resistance element R22 from the node N5 anda resistance value of the resistance element R22.

Because the switch element SW24 is turned ON, the resistance elementSW23 is coupled to the node N4 through which no current flows. Even whenthe switch element SW24 is turned OFF next time, and when the switchelement SW23 is turned ON, it is possible to have a constant load of thenode N4 by the resistance element.

In this manner, in the current detection circuit 20 according to thisembodiment, like the case of the current detection circuit 10, theoperational amplifier A1 amplifies a potential difference between thedrain voltage of the transistor Tr1 and the drain voltage of thetransistor MN1. As a result, even when the transistor Tr1 is switchedbetween ON/OFF states quickly, the voltage to be supplied to the inputterminal of the operational amplifier A1 is not quickly switched. Thus,the operational amplifier A1 is not required to perform a high-speedoperation. In the current detection circuit 20 according to thisembodiment, the operational amplifier A2 amplifies the potentialdifference between the source voltage of the transistor Tr2 and thesource voltage of the transistor MN4. Thus, even when the transistor Tr2is switched between ON/OFF states quickly, the operational amplifier A2is not required to perform a high speed operation, because the voltagesupplied to the input terminal of the operational amplifier A2 is notquickly switched. Thus, the current detection circuit 20 does not needto use the expensive operational amplifier for the operationalamplifiers A1 and A2, thereby enabling to suppress the increase in themanufacturing cost.

In the current detection circuit 20 according to this embodiment, likethe current detection circuit 10, it is adjusted that a potentialdifference between a high potential side source voltage (a voltageVhigh) and a low potential side source voltage (an input voltage Vin)supplied to the operational amplifier A1 becomes equal to or lower thana withstand voltage of each transistor included in this operationalamplifier A1. Thus, the operational amplifier A1 may be configured notonly with a high withstand voltage transistor, but also with a lowwithstand voltage transistor. As a result, it is possible to improve theaccuracy or the operational speed of the operational amplifier A1. Theoperational amplifier A2 is configured with the low withstand voltagetransistor, thereby enabling to perform the high speed operation withhigh accuracy.

In this embodiment, the descriptions have been made to the example inwhich the configuration of the circuit detecting the current flowingthrough the transistor Tr1 in the circuit configuration of the currentdetection circuit 20 is the same as the configuration of the currentdetection circuit 10 c. However, it is not limited to this example. Theconfiguration of the circuit detecting the current flowing through thetransistor Tr1 in the circuit configuration of the current detectioncircuit 20 may be the same as the configuration of any of the currentdetection circuits 10, 10 a, and 10 b.

(Application Example of Current Detection Circuit 20)

FIG. 10 is a diagram illustrating a configuration example of astep-up/step-down DCDC converter 2 in which the current detectioncircuit 20 is mounted. FIG. 11 is a timing chart illustrating anoperation of the DCDC converter 2. The DCDC converter 2 uses an averagecurrent mode control system as one control system for the outputvoltage.

As illustrated in FIG. 10, the DCDC converter 2 includes the currentdetection circuit 20, the drive circuit 22, and a control unit 21. Thedrive circuit 22 includes transistors Tr1 to Tr4, the inductor L1, thecapacitance element C1, and the resistance elements R11 and R12. Thecontrol unit 21 has error amplifiers EA1 and EA2, capacitance elementsC2 to C5, resistance elements R3 and R5, a level-down circuit LD1,comparator CMP 21 and CMP 22, buffers BF1 and BF2, and inverters INV1and INV2.

In the drive circuit 22, the transistor (a third drive transistor) Tr3is provided between the other end (the node N2) and the output terminalOUT of the inductor L1, and a pulse signal P3 is supplied to its gatefrom the control unit 21. The transistor Tr4 (a fourth drive transistor)is provided between the other end and the ground voltage terminal GND ofthe inductor L1, and a pulse signal P4 is supplied to its gate from thecontrol unit 21. Any other configurations of the drive circuit 22 arethe same as those of the drive circuit 12, and thus will not bedescribed repeatedly over and over.

In the step-down operation of the drive circuit 22, the transistor Tr3is fixed in the ON state, and the transistor Tr4 is fixed in the OFFstate. Then, the transistors Tr1 and Tr2 are controlled between ON/OFFstates complementarily based on the dead time existing therebetween.

In the step-down operation of the drive circuit 22, the transistor Tr1is turned ON, and the transistor Tr2 is turned OFF, thereby causing acurrent to flow from the input terminal IN to the output terminal OUTthrough the transistor Tr1 and the inductor L1. At this time, theinductor L1 is charged with current energy. After this, the transistorTr1 is turned OFF, and the transistor Tr2 is turned ON, thereby cuttingoff the current flowing from the input terminal IN to the inductor L1through the transistor Tr1. To maintain the current value of thepreviously flowing current, the inductor L1 discharges the chargedcurrent energy toward the output terminal OUT. As a result, a currentflows from the ground voltage terminal GND toward the output terminalOUT through the transistor Tr2. By repeating this operation, the drivecircuit 22 outputs an output voltage Vout which is obtained by steppingdown the input voltage Vin by a certain level corresponding to a dutyratio of pulse signals P1 and P2.

In the step-up operation of the drive circuit 22, the transistor Tr1 isfixed in the ON state, and the transistor Tr2 is fixed in the OFF state.Then, the transistors Tr3 and Tr4 are controlled complementarily basedon the dead time existing therebetween.

In the step-up operation of the drive circuit 22, first, the transistorTr4 is turned ON, and the transistor Tr3 is turned OFF, thereby causinga current to flow from the input terminal IN to the ground voltageterminal GND through the inductor L1 and the transistor Tr4. At thistime, the inductor L1 is charged with current energy. After this, thetransistor Tr4 is turned OFF, and the transistor Tr3 is turned ON,thereby cutting off the current flowing from the inductor L1 to theground voltage terminal GND through the transistor Tr4. To maintain thecurrent value of the previously flowing current, the inductor L1discharges the charged current energy toward the output terminal OUT. Byrepeating this operation, the drive circuit 22 outputs an output voltageVout which is obtained by stepping up the input voltage Vin by a certainlevel corresponding to a duty ratio of pulse signals P3 and P4.

Further, in the step-up/step-down operation of the drive circuit 22, theabove-described step-up operation and the step-down operation areperformed in combination with each other.

As described above, the current detection circuit 20 detects the currentflowing through the transistor Tr1 provided on the high side of thedrive circuit 22, and detects the current flowing through the transistorTr2 provided on the low side of the drive circuit 22, thereby detectingthe current flowing through the inductor L1 and outputting a detectionresult Vcs. This detection result Vcs is fed back to the control unit21.

In the control unit 21, the error amplifier EA1 amplifies a potentialdifference between the reference voltage Vref and the voltage Vfb fedback from the drive circuit 22, to generate a voltage Vc. The voltage Vcis integrated by the capacitance element C2 provided between the outputterminal and the ground voltage terminal GND of the error amplifier EA1,and the capacitance element C3 and the resistance element R3 provided inseries between the output terminal and the ground voltage terminal GNDof the error amplifier EA1.

For example, when the output voltage Vout decreases, and when thevoltage Vfb is lower than the reference voltage Vref, the output voltageVc of the error amplifier EA1 increases at the rate proportional to thepotential difference between the voltage Vfb and the reference Vref. Onthe contrary, when the output voltage Vout increases, and when theoutput voltage Vfb is higher than the reference voltage Vref, the outputvoltage Vc of the error amplifier EA1 decreases at the rate proportionalto the potential difference between the voltage Vfb and the referencevoltage Vref. In the example of FIG. 11, the potential differencebetween the output voltage Vout and the reference voltage Vref is small.Thus, the output voltage Vc of the error amplifier EA1 indicates aconstant value.

The error amplifier EA2 amplifies a potential difference between anoutput voltage (a reference voltage for the error amplifier EA2) of theerror amplifier EA1 and a detection result Vcs of the current detectioncircuit 20, to generate a voltage VR1. The voltage VR1 is integrated bythe capacitance element C4 provided between the output terminal and theground voltage terminal GND of the error amplifier EA2 or by thecapacitance element C5 and the resistance element R5 which are providedin series between the output terminal and the ground voltage terminalGND of the error amplifier EA2.

For example, when the current flowing through the inductor L1 decreases,and when the detection result Vcs is lower than the voltage Vc, theoutput voltage VR1 of the error amplifier EA2 increases at the rateproportional to the potential difference between the detection resultVcs and the voltage Vc. On the contrary, when the current flowingthrough the inductor L1 increases, and when the detection result Vcs ishigher than the voltage Vc, the output voltage VR1 of the erroramplifier EA2 decreases at the rate proportional to the potentialdifference between the detection result Vcs and the voltage Vs. In theexample of FIG. 11, the output voltage VR1 of the error amplifier EA2gradually increases while reducing the increasing rate, in accordancewith the gradual increase of the detection result Vcs.

The level down circuit LD1 reduces the voltage VR1 by a predeterminedvoltage, and outputs it as a voltage VR1.

The comparator CMP21 compares the voltage VR1 and a triangular wave Vrr,and outputs a comparison result Vbuck. The buffer BF1 outputs thecomparison result Vbuck as is as a pulse signal P1. The inverter INV1inverts the comparison result Vbuck and outputs it as a pulse signal P2.

The comparator CMP22 compares the voltage VR2 and the triangular waveVrr, and outputs it as a comparison result Vboost. The inverter INV2inverts the comparison result Vboost, and outputs it as a pulse signalP3. The buffer BF2 outputs the comparison result Vboost as is as a pulsesignal P4.

With reference to FIG. 11, when the transistor Tr1 is turned ON, andalso when the transistor Tr2 is turned OFF, the current flowing throughthe inductor L1 increases, thus increasing the detection result Vcs ofthe current detection circuit 20. On the contrary, when the transistorTr2 is turned ON, and when the transistor Tr1 is OFF, the currentflowing through the inductor L1 decreases, the detection result Vcs ofthe current detection circuit 20 decreases. This detection result Vcsgradually increases totally while repeating the increase and thedecrease. In accordance with it, the output voltage VR and the voltageVR2 of the error amplifier EA2 gradually increase while reducing theincreasing rate.

In the example of FIG. 11, the triangular wave Vrr goes up and downaround the voltage VR1, and always indicates a value higher than thevoltage VR2. The comparison result Vbuck of the comparator CMP21 isrepeatedly switched between the H level and the L level, while thecomparison result Vboost of the comparator CMP22 is fixed in the Llevel. That is, in the example of FIG. 11, the step-up operation is notperformed, but only the step-down operation is performed.

For example, when the voltage VR1 is higher than the triangular Vrr, thecomparator CMP21 outputs the comparison result Vbuck with the H level.Thus, the transistor Tr1 is turned ON, and the transistor Tr2 is turnedOFF. Then, because the current flowing through the inductor L1increases, the potential of the detection result Vcs increases inproportion to the elapse of the time in which the current flows. On thecontrary, when the voltage VR1 is equal to or lower than the triangularwave Vrr, the comparator CMP21 outputs the comparison result Vbuck withthe L level. Thus, the transistor Tr1 is turned OFF, and the transistorTr2 is turned ON. Then, the current flowing through the inductor L1decreases, thereby decreasing the potential of the detection result Vcsproportional to the elapse of the time in which this current flows. Byrepeating this operation, the DCDC converter 2 steps down (or steps up)the input voltage Vin to a predetermined level, and outputs it as anoutput voltage Vout.

This DCDC converter 2 is mounted, for example, over the vehicles. Inrecent years, the DCDC converter mounted over the vehicle is required toperform a high speed switching operation. Thus, it is effective to applythe current detection circuit 20 without being effected by the highspeed switching operation. Further, the current detection circuit 20 canrealize the operation with high accuracy by using the operationalamplifiers A1 and A2 configured with a low withstand transistor. In thiscase, it is possible to design the DCDC converter 2 on the assumptionthat the accuracy variation is small. The DCDC converter 2 can increasethe loop band.

Subsequently, descriptions will hereinafter be made to somemodifications of the current detection circuit 20.

(First Modification of Current Detection Circuit 20)

FIG. 12 is a diagram illustrating a first modification of the currentdetection circuit 20 as a current detection circuit 20 a.

In the current detection circuit 20 a illustrated in FIG. 12, ascompared with the current detection circuit 20 illustrated in FIG. 10,there is further provided a voltage supply unit for supplying a voltagehigher than the ground voltage GND to one input terminal coupled to theground voltage terminal GND, of two input terminals of the operationalamplifier A2.

The voltage supply unit has a transistor MN6 and a constant currentsource (a second constant current source) CC2.

The transistor MN6 is configured with the high withstand voltageN-channel MOS transistor having the same size as, for example, thetransistor MN4. The transistor MN6 is provided between one inputterminal (non-inverted input terminal) of the operational amplifier A2and the ground voltage terminal GND, and a source voltage VDD issupplied to its gate, thereby always being in the ON state. That is, thetransistor MN6 functions as a resistance element (a second resistanceelement).

The constant current source CC2 is provided between the source voltageterminal VDD and one input terminal of the operational amplifier A2, andsupplies a constant current to the one input terminal of the operationalamplifier A2. As a result, a voltage which is higher by a predeterminedvoltage than the ground voltage GND is supplied to the one inputterminal of the operational amplifier A2. Any other configurations ofthe current detection circuit 20 a are the same as those of the currentdetection circuit 20, and thus will not be described repeatedly over andover.

The source voltage of the transistor MN4 may and should originally belower than the drain voltage, by the effect of the offset voltage of theoperational amplifier A2. However, if the voltage supply unit is notprovided, the voltage of the other input terminal (inverted inputterminal) of the operational amplifier A2 cannot be a minus voltagelower than the ground voltage GND supplied to the one input terminal(non inverted input terminal). Thus, the source voltage of thetransistor MN4 will not be lower than assumed. As a result, it is notpossible to perform current detection in consideration of the effect ofthe offset voltage.

On the contrary, the current detection circuit 20 a supplies a voltagehigher than the ground voltage GND to the one input terminal of theoperational amplifier A2 using the voltage supply unit. As a result, inthe current detection circuit 20 a, the source voltage of the transistorMN4 can be lower than the drain voltage as assumed, by the effect of theoffset voltage, thus enabling to perform current detection inconsideration of the offset voltage.

(Second Modification of Current Detection Circuit 20)

FIG. 13 is a diagram illustrating a second modification of the currentdetection circuit 20 as a current detection circuit 20 b.

As compared with the current detection circuit 20 illustrated in FIG. 7,the current detection circuit 20 b illustrated in FIG. 13 furtherincludes a transistor (a switch transistor) MN7.

The transistor MN7 is configured with a high withstand voltage N-channelMOS transistor having the same size as, for example, the transistor MN4.The transistor MN7 is provided between the two input terminals of theoperational amplifier A2. The transistor MN7 is controlled to be turnedON/OFF based on the inverted signal P2B of the pulse signal P2. That is,the transistor MN7 is controlled to be turned ON/OFF complementarilywith the transistors Tr2 and MN4. The resistance value at the time thetransistor MN7 is turned ON indicates the same resistance value at thetime the transistor MN4 is turned ON. Any other configurations of thecurrent detection circuit 20 b are the same as those of the currentdetection circuit 20, and thus will not be described repeatedly over andover.

Even if the transistor MN4 is turned OFF, the transistor MN7 is turnedON. Thus, the load of the operational amplifier A2 by the resistanceelement is constantly maintained. As a result, the current detectioncircuit 20 b can suppress the settling time of the operational amplifierA2 after the transistor MN4 is switched between ON/OFF states, therebyrealizing the high-speed operation.

Third Embodiment of Current Detection Circuit 20

FIG. 14 is a diagram illustrating a third modification of the currentdetection circuit 20 as a current detection circuit 20 c.

As compared with the current detection circuit 20 illustrated in FIG. 7,the current detection circuit 20 c illustrated in FIG. 14 furtherincludes a voltage supply unit for supplying a voltage higher than theground voltage GND to one input terminal of the operational amplifierA2, and also includes the transistor MN7 provided between the two inputterminals of the operational amplifier A2. That is, the currentdetection circuit 20 c includes the constituent element added into thecurrent detection circuit 20 a and the constituent element added intothe current detection circuit 20 b.

As a result, in the current detection circuit 20 c, the source voltageof the transistor MN4 can be lower than the drain voltage as assumed bythe effect of the offset voltage, thus enabling to perform currentdetection in consideration of the offset voltage. The current detectioncircuit 20 c can suppress the settling time of the operational amplifierA2 after the transistor MN4 is switched between ON/OFF states, therebyrealizing the high speed operation.

Embodiment 3

In this embodiment, descriptions will now be made to another applicationexample of the current detection circuit 20.

FIG. 15 is a diagram illustrating a configuration example of astep-up/step-down DCDC converter 3 on which the current detectioncircuit 20 is mounted.

As illustrated in FIG. 15, the DCDC converter 3 includes the currentdetection circuit 20, the drive circuit 22, and a control unit 31. Thecurrent detection circuit 20 and the drive circuit 22 have already beendescribed. The control unit 31 will hereinafter be described.

The control unit 31 includes a PID control unit 111, a PI control unit112, a PWM generation unit 113, a filter 115, a step-up/step-downdetermination unit (a determination unit) 116, subtracters 117 and 118,a memory unit 119, a multiplier 120, a selection circuit 121, aresistance element 122, a subtracter 123, an adder 124, a divider 125,buffers BF1 and BF2, and inverters INV1 and INV2.

The subtracter 117 outputs a difference between a reference voltage Vrefand a voltage Vfb fed back from the drive circuit 22, as a differencesignal e.

The PID control unit 111 is a circuit for feedback controlling an outputvoltage Vout, performs PID control (proportional control, integralcontrol, differential control) for the difference signal e output fromthe subtracter 117, and outputs it as a control signal S.

In the PID control unit 111, the proportional control, the integralcontrol, and the differential control for the difference signal e areperformed based on the following equations (1) and (2). In this case,“KP” represents a reference proportional constant, “KI” represents anintegral constant, “KD” represents a differential constant, and “t”represents the time.

Proportional control:KP*e(t)  (1)

Integral control:KI*∫e(t)dt  (2)

Differential control:KD*d/dt·e(t)  (3)

The PID control unit 111 adds a result of adding the proportionalcontrol, the integral control, and the differential control for thedifference signal e, and outputs it as a control signal S.

The filter 115 removes a noise component of the detection result Vcs ofthe current detection circuit 20.

The subtracter 118 outputs a difference between the control signal Soutput from the PID control unit 111 and a result of filtering thedetection result Vcs of the current detection circuit 20 by the filter115, as a difference signal ei.

The PI control unit 112 is a circuit for feedback controlling theaverage current flowing through the inductor L1, performs PI control(proportional control and integral control) for the difference signal eioutput from the subtracter 118, and outputs it as a control signal D.

At the time of voltage step down, that is, at the time when the inputvoltage Vinthe output voltage Vout, the average current flowing throughthe inductor L1 is proportional to the input voltage Vin. Therefore, ifno countermeasure is made, the current loop band for feedbackcontrolling the current flowing through the inductor L1 will beproportional to the input voltage. As a result, it is difficult that theband of the current loop is widened.

In consideration of the above, the present inventors have focused onthat the control signal D is inversely proportional to the input voltageVin during the voltage step down. They have adopted a configuration,during the voltage step down, for proportionally controlling thedifference signal ei using a proportional constant which has beenobtained by multiplying the reference proportional constant KP by thecontrol signal D and dividing it by an error component Err. As a result,in the DCDC converter 3, during the voltage step down, the input voltagedependency of the current loop band is offset. Thus, it is possible togenerate a stable output voltage Vout, without depending on the level ofthe input voltage Vin. Note, during the voltage step up, the currentloop band has no input voltage dependency.

Specifically, the step-up/step-down determination unit 116 determineswhether the drive circuit 22 is now in the process of stepping up orstepping down a voltage, based on the control signal D output from thePI control unit 112. The divider 125 outputs a result D/Err which hasbeen obtained by dividing the control signal D by the error componentErr. The error component Err is an added result by the adder 124. Thisadded result is obtained by adding a difference (Vset−e) and a voltage(Iout*Rp). This difference is a difference between a difference signal ecalculated by the subtracter 123 and a target voltage Vset of the outputvoltage Vout. The voltage is generated by a current Iout, flowingthrough the inductor L1 and obtained based on the detection result Vcs,and a parasitic resistance Rp of the drive line.

The multiplier 120 outputs a multiplied result KP*D/Err which has beenobtained by multiplying the output D/Err of the divider 125 and areference proportional constant KP stored in the memory unit 119. Theselection circuit 121 selects and outputs either one of the referenceproportional constant KP and the multiplied result KP*D/Err, based onthe determination result of the step-up/step-down determination unit116. For example, when the step-up/step-down determination unit 116determines that it is in the process of stepping up a voltage (orstepping-up/stepping down), the selection circuit 121 selects andoutputs the reference proportional constant KP. On the contrary, whenthe step-up/step-down determination unit 116 determines that it is inthe process of stepping down the voltage, the selection circuit 121selects and outputs the multiplied result KP*D/Err.

The output result of the selection circuit 121 is used as a proportionalconstant in the proportional control of the PI control unit 112. Thatis, the PI control unit 112 performs proportional control for thedifference signal ei using the reference proportional constant KP as aproportional constant, during the voltage step up, and performsproportional control for the difference signal ei using the multipliedresult KP*D/Err as a proportional constant, during voltage step down.

In the PI control unit 112, the proportional control and the integralcontrol for the difference signal ei are performed respectively based onthe following equations (4) and (5).

Proportional control(during voltage step up):KP*ei(t)

(during voltage step down):KP*D/Err*ei(t)

Integral control:KI*∫ei(t)dt  (5)

The PI control unit 112 adds results of the proportional control and theintegral control for the difference signal ei, and then outputs theaddition result as a control signal D.

The PWM generation unit 113 generates pulse signals Vbuck and Vboost ofthe duty ratio of the control signal D. The buffer BF1 outputs the pulsesignal Vbuck as is as a pulse signal P1. The inverter INV1 inverts thepulse signal Vbuck, and outputs it as a pulse signal P2. The inverterINV2 inverts the pulse signal Vboost, and outputs it as a pulse signalP3.

In this manner, the DCDC converter 3 according to this embodimentproportionally controls the difference signal ei (a current loop) usinga proportional constant, during the voltage step down. This proportionalconstant has been obtained by multiplying the control signal D inverselyproportional to the input voltage Vin and the error component Err. As aresult, the DCDC converter 3 can offset the input voltage dependency ofthe current loop band, during the voltage step down, thereby enabling towidening the band of the current loop entirely over the input power. Itis possible to realize widening of the band of the current loop forfeedback controlling the output voltage Vout, together with the wideningof the band of the current loop. As a result, the DCDC converter 3 cangenerate the stable output voltage Vout without depending on the inputvoltage Vin. In other words, it is possible to improve the LineTransient characteristic and the Load Transient characteristic.

In this embodiment, though the descriptions have so far been made to thecase in which the DCDC converter 3 is a step-up/step-down converter.However, it is not limited to this type, and it may simply have afunction for at least stepping up the voltage.

The PID control unit 111 may be replaced by a PI control unit whichperforms only the proportional control and the integral control.

The PI control unit 112 may be replaced by a PID control unit whichperforms the differential control, in addition to the proportionalcontrol and the integral control.

Further, during the voltage step down, the PI control unit 112 mayperform not only proportional control using the proportional constantmultiplied by D/Err, but also perform the integral control using theintegral constant multiplied by D/Err. Further, when the PI control unit112 is replaced by the PID control unit, during the voltage step down,the differential control may be performed using the differentialconstant multiplied by D/Err.

As described above, in the current detection circuits 10 and 20according to the above-described embodiments 1 to 3, the operationalamplifier A1 amplifies the potential difference between the drainvoltage of the transistor Tr1 and the drain voltage of the transistorMN1, instead of amplifying the potential difference between the sourcevoltage of the transistor Tr1 and the source voltage of the transistorMN1. As a result, even when the transistor Tr1 is switched quicklybetween the ON/OFF states, the voltage supplied to the input terminal ofthe operational amplifier A1 is not quickly switched. Thus, theoperational amplifier A1 is not required to perform the high speedoperation. Therefore, the current detection circuits 10 and 20 accordingto the above-described embodiments 1 to 3 do not need to use theexpensive operational amplifier for the operational amplifier A1,thereby enabling to suppress an increase in the manufacturing cost.

In the current detection circuits 10 and 20 according to theabove-described embodiments 1 to 3, it is adjusted that the potentialdifference between the high potential side source voltage (a voltageVhigh) and the low potential side source voltage (an input voltage Vin)supplied to the operational amplifier A1 becomes equal to or lower thana withstand voltage of each transistor included in the operationalamplifier A1. Thus, it is not limited that the operational amplifier A1is configured with the high withstand voltage transistor, and may beconfigured with a low withstand voltage transistor. Thus, it is possibleto improve the accuracy or the operational speed of the operationalamplifier A1.

Further, in the current detection circuit 20 according to theabove-described embodiments 2 and 3, the operational amplifier A2amplifies the potential difference between the source voltage of thetransistor Tr2 and the source voltage of the transistor MN4. Even whenthe transistor Tr2 is quickly switched between the ON/OFF states, thevoltage supplied to the input terminal of the operational amplifier A2is not quickly switched. Thus, the operational amplifier A2 is notrequired to perform the highspeed operation. As a result, the currentdetection circuit 20 according to the above-described embodiments 2 and3 does not need to use the expensive operational amplifier for theoperational amplifier A2, thereby enabling to suppress the increase inthe manufacturing cost.

In the above-described embodiments 1 to 3, the descriptions have beenmade to the case in which the current detection circuit is mounted overthe DCDC converter. However, it is not limited to this example. Forexample, the circuit may be mounted over the solenoid driver or themotor control device.

Accordingly, the inventions made by the present inventors havespecifically been described based on the preferred embodiments. Thepresent invention is not limited to the above-described embodiments.Various changes may be made without departing from the scope thereof.

For example, in the configuration of the semiconductor memory deviceaccording to the above-described embodiments, it is possible to invertthe conductive type (p-type or n-type) of the semiconductor substrate,the semiconductor layer, and the diffusion layer (diffusion area). Whenone of the conductive types of the n-type and p-type is assumed as afirst conductive type, and the other conductive type is assumed as asecond conductive type, the first conductive type may be the p-type,while the second conductive type may be the n-type. On the contrary, thefirst conductive type may be the n-type, while the second conductivetype may be the p-type.

What is claimed is:
 1. A DCDC converter comprising: a drive circuit; acurrent detection circuit configured to detect a value of a currentflowing through a first drive transistor; a first comparator configuredto compare a detection result of the current detection circuit and areference voltage; and a pulse signal generation unit configured togenerate a pulse signal of a duty ratio in accordance with a comparisonresult of the first comparator, wherein the drive circuit has a seconddrive transistor provided on a low side, and being controlled to beturned ON/OFF based on a dead time existing therebetween complementarilywith the first drive transistor in accordance with a pulse signal, andan inductor provided between the first and second drive transistors andthe external output terminal.
 2. A DCDC converter comprising: a drivecircuit; a current detection circuit configured to a value of a currentflowing through an inductor; an error amplifier which amplifies adifference between a detection result of the current detection circuitand a reference voltage; and a pulse signal generation circuit whichgenerates first and second pulse signals of a duty ratio in accordancewith an output result of the error amplifier, wherein the drive circuithas the inductor, a first drive transistor configured to control acurrent flowing from an external input terminal to an external outputterminal through the inductor, by being controlled to be turned ON/OFFbased on a first pulse signal, during voltage step down, a second drivetransistor configured to control a current flowing from a ground voltageterminal to the external output terminal through the inductor, by beingcontrolled to be turned ON/OFF based on a dead time existingtherebetween complementarily with the first drive transistor, during thevoltage step down, a third drive transistor configured to control acurrent flowing from the external input terminal to the ground voltageterminal through the inductor, by being controlled to be turned ON/OFFbased on a second pulse signal, during voltage step up, and a fourthdrive transistor configured to control a current flowing from theexternal input terminal to the external output terminal through theinductor, by being controlled to be turned ON/OFF based on a dead timeexisting therebetween complementarily with the third drive transistor,during voltage step up.